this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. rev.0 2 / j an .9 9 hyundai semiconductor hy63 v 8 1 00 a series 128kx8bit cmos fas t sram preliminary description the hy63 v 8 1 00 a is a 1,048,576 -bit high-speed , sram organized as 131,072 words by 8-bits. the hy63 v 8 1 00 a uses eight common input and output lines and has an output enable pin which operates faster than. address access time at read cycle. the device is fabricated using hyundai's advanced cmos process and designed for high-speed circuit technology. it is particularly well suited for use in high-density high-speed system applications features single 3.3v 0.3v power supply fully static operation and tri-state output ttl compatible inputs and outputs low data retention voltage: - 2.0v(min) ? l-ver. only center power/ground pin configuration standard pin configuration - 32pin 400mil soj /tsop- ll product supply speed operation standby current( m a) no. voltage(v) ( ns) current( ma) l hy63v 81 00 a 3.3 8 200 5 0.5 hy63v 81 00 a 3.3 10 190 5 0.5 hy63v 8 100 a 3.3 12 180 5 0.5 pin connection block diagram soj/tsop2 pin description pin name pin fun c tion pin name pin fun c tion /cs chip select a0~a16 address input /we write enable vcc power(+3.3v) /oe output enable vss ground i/o1~i/o8 data input s /output s n . c no connection row decoder memory array 512x256x8 sense amp write driver output buffer i/o1 i/o8 decoder add input buffer a0 a16 / cs / oe / we a10 a16 a15 / oe i/o8 i/o7 vss vcc i/o6 i/o5 a11 a9 a8 a0 a1 a2 a3 a4 / cs i/o1 i/o2 i/o3 i/o4 vcc vss / we a5 a6 a7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 soj/ tsop2 a14 a13 a12
hy63 v 8 100a series rev.0 2 / j an .9 9 2 absolute maximum ratings(1) symbol parameter rating unit v in, v out voltage on any pin relative to vss -0.5 to 4.6 v vcc voltage on vcc supply relative to vss -0.5 to 5.5 v commercial 0 to 70 c t a operating temperature industrial -40 to 85 c t stg storage temperature -65 to 150 c p d power dissipation 1.0 w note 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational of this specification is not implied. exposure to absolute maximum rating conditions for extended period may affect reliability. recommended dc operating conditions ( t a =0 c to 70 c) symbol parameter min. type max. unit vcc supply voltage 3.0 3 . 3 3 . 6 v vss ground 0 0 0 v v ih input high voltage 2. 0 - vcc+0. 3(2) v v il input low voltage -0. 3(1) - 0.8 v note 1. v il (min) = - 2 .0v a.c ( pulse width less than 8ns) for i < 20ma 2. v ih (max) = vcc + 2.0v a.c( pulse width less than 8ns) for i < 20ma dc electrical characteristics ( vcc = 3 . 3 v 0.3v , t a = 0 c to 70 c , unless otherwise specified. ) symbol parameter test conditions min typ max unit i li input leakage current v ss < v in < v cc -2 - 2 ua i lo output leakage current v ss < v out < v cc , /cs = v ih or / oe = v ih or /we = v il -2 - 2 ua /cs = v il , v in = v ih , 8ns - - 200 ma i cc operating current i i/o = 0ma 1 0 ns - - 190 ma min. duty cycle = 100% 1 2ns - - 180 ma i sb ttl standby current (ttl inputs) /cs = v ih, v in= v ih or v il min. cycle - - 60 ma i sb1 cmos standby current /cs > v cc -0.2v, v in > - - 5 ma (cmos inputs) v cc -0.2v or v in < 0.2v l - 0.5 ma v ol output low voltage i ol = 8.0ma - - 0.4 v v oh output high voltage i oh = -4.0ma 2.4 - - v note : typical values are at vcc = 3. 3 v, t a = 25 c
hy63 v 8 100a series rev.0 2 / j an .9 9 3 ac characteristics ( vcc = 3 . 3 v 0.3v , t a = 0 c to 70 c , unless otherwise specified. ) 8 ns 10 ns 12 ns # symbol parameter min max min max min max unit read cycle 1 t rc read cycle time 8 - 10 - 12 - ns 2 taa address access time - 8 - 1 0 - 12 ns 3 t acs chip select access time - 8 - 1 0 - 1 2 ns 4 toe output enable to output valid - 4 - 5 - 6 ns 5 t clz chip select to output in low z 3 - 3 - 3 - ns 6 tolz output enable to output in low z 0 - 0 - 0 - ns 7 tchz chip deselecting to output in high z 0 5 0 5 0 6 n s 8 tohz out disable to output in high z 0 5 0 5 0 6 ns 9 toh output hold from address change 3 - 3 - 3 - ns write cycle 10 twc write cycle time 8 - 10 - 12 - ns 11 tcw chip select to end of write 6 - 7 - 8 - ns 12 t aw address valid to end of write 6 - 7 - 8 - ns 13 tas address set-up time 0 - 0 - 0 - ns 14 twp write pulse width (/oe high) 6 - 7 - 8 - ns 15 twp1 write pulse width (/oe low) 8 - 10 - 12 - ns 16 twr write recovery time 0 - 0 - 0 - ns 17 t whz write to output in high z 0 4 0 5 0 6 ns 18 tdw data to write time overlap 4 - 5 - 6 - ns 19 tdh data hold from write time 0 - 0 - 0 - ns 20 tow output active from end of write 3 - 3 - 3 - ns note : above parameters are also guaranteed at industrial temperature range.
hy63 v 8 100a series rev.0 2 / j an .9 9 4 ac test conditions ( vcc = 3.3 v 0.3v , t a = 0 c to 70 c , unless otherwise specified. ) parameter value input pulse level 0v to 3v input rise and fall time 3ns input and output timing reference level 1.5v output load see below ac test conditions output load (a) output load (b) ( for tchz, tclz, tohz, tolz, twhz & tow) note : * including jig and scope capacitance capacitance temp = 25 c , f= 1.0mhz symbol parameter condition max. unit cin input capacitance v in = 0v 7 pf c i/o input/output capacitance v i/o = 0v 8 pf note : this parameter is sampled and not 100% tested dout r l =50 w z o = 50 w v l = 1.5 v dout 353 w 5 pf * + 3.3 v
hy63 v 8 100a series rev.0 2 / j an .9 9 5 timing diagram read cycle 1 addr oe cs data out data valid trc tacs tclz toe tolz taa toh tohz tchz high-z note (read cycle) 1. tchz and tohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, tchz max. is less than tclz min. both for a given device and from device to device. 3. /we is high for read cycle. read cycle 2 trc taa data valid previous data toh toh addr data out note (read cycle) 1. /we is high for read cycle. 2. device is continuously selected /cs=v il . 3. /oe=v il .
hy63 v 8 100a series rev.0 2 / j an .9 9 6 write cycle 1(/oe clocked) addr oe cs data out twc tdw tohz we data valid tdh twp tas data in twr tcw taw write cycle 2(/oe low fixed) tdw twhz we data valid tdh twp tas data in twr tcw taw (7) (8) tow addr cs data out twc notes(write cycle) 1. a write occurs during the overlap of a low /cs and a low /we. a write begins at the latest transition among /cs going low, and /we going low : a write ends at the earliest transition among /cs going high and /we going high. twp is measured from the beginning of write to the end of write. 2. tcw is measured from the later of /cs going low to end of write. 3. tas is measured from the address valid to the beginning of write. 4. twr is measured from the end of write to the address change. twr applied in case a write ends as /cs or /we going high. 5. if /oe and / we are in the read mode during this period, the i/o pins are in the output low-z state, inputs of opposite phase of the output must not be applied because bus contention can occur. 6. if /cs goes low simultaneously with / we going low or after /we going low, the outputs remain in high impedance state. 7. d out is the same phase of latest written data in the write cycle. 8. d out is the read data of the new address.
hy63 v 8 100a series rev.0 2 / j an .9 9 7 functional description i/o pin /cs /we /oe /lb /ub mode i/o1 - i/o8 i/o9 - i/o16 supply current h x x* x x not select high-z high-z isb,isb1 l h h x x l x x h h output disable high-z high-z icc l h dout high-z h l high-z dout l h l l l read dout dout icc l h din high-z h l high-z din l l x l l write din din icc * note : x means don,t care data retention electric charateristic ( t a = 0 c to 70 c ) symbol parameter test condition min typ max unit v dr vcc for data retention /cs > vcc - 0.2v 2 .0 - 3.6 v vcc = 3.0v, /cs > vcc - 0.2v vin > vcc - 0.2v or < 2 .0v - - 0.9 i dr data retention current vcc = 2 .0v, /cs > vcc - 0.2v vin > vcc - 0.2v or < 2 .0v - - 0.7 m a tc dr data retention set-up time 0 - - ns tr recovery time 5 - - ms data retention timing diagram cs vdr cs > vcc-0.2v tcdr tr vss vcc 3.0/2.7v 2.2v data retention mode
hy63 v 8 100a series rev.0 2 / j an .9 9 8 package information 32pin 400mil small outline j-form package (j) 0.026(0.66) 0.032(0.81) 0.395(10.033) 0.829(21.0566) 0.030(0.762) 0.368(9.3472) 0.380(9.65) 0.436(11.0744) 0.444(11.2776) 0.138(3.505) 0.016(0.41) 0.020(0.508) 0.050(1.27) bsc. 0.821(20.8534) unit : inch(mm) 0.405(10.287) 0.148(3.759) 0.040(1.016) 32pin 400mil thin small outline package (t2) 10.2620(0.404) 10.0580(0.396) 11.9380(0.470) 11.7350(0.462) 21.0570(0.829) 20.8790(0.822) 1.2700 bsc (0.050) 0.4500(0.017) 0.3050(0.012) base plane seating plane 1.1940(0.047) 0.9910(0.039) 0.1500(0.0059) 0.0500(0.0020) 0.2100(0.0083) 0.1200(0.0047) 0.5970(0.0235) 0.4060(0.0160) gage plane 0-5 unit : inch(mm) max. min.
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